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SI9160
Vishay Siliconix
Controller for RF Power Amplifier Boost Converter
FEATURES
D High Frequency Switching (up to 2 MHz) D Optimized Output Drive Current (350 mA) D Standby Mode D Wide Bandwidth Feedback Amplifier D Single-Cell LiIon and Three-cell NiCd or NiMH Operation
DESCRIPTION
The SI9160 Controller for RF Power Amplifier Boost Converter is a fixed-frequency, pulse-width-modulated power conversion controller designed for use with the Si6801 application specific MOSFET. The SI9160 and the Si6801 are optimized for high efficiency switched-mode power conversion at 1 MHz and over. The device has an enable pin which can be used to put the converter in a low-current mode compatible with the standby mode of most cellular phones. A wide bandwidth feedback amplifier minimizes transient response time allowing the device to meet the instantaneous current demands of today's digital protocols. The input voltage range accommodates minimal size and cost battery pack configurations. Frequency control in switching is important to noise management techniques in RF communications. The SI9160 is easily synchronized for high efficiency power conversion at frequencies in excess of 1 MHz. Optimizing the controller and the synchronous FETs results in the highest conversion efficiency over a wide load range at the switching frequencies of interest (1 MHz or greater). It also minimizes the overshoot and gate ringing associated with drive current and gate charge mismatches. When disabled, the converter requires less than 330 mA. This capability minimizes the impact of the converter on battery life when the phone is in the standby mode. Finally, operating voltage is optimized for LiIon battery operation (2.7 V to 4.5 V) and can also be used with three-cell NiCd or NiMH (3 V to 3.6 V), as well as four-cell NiCd or NiMH (4 V to 4.8 V) battery packs. The SI9160 is available in both standard and lead (Pb)-free packages.
APPLICATION CIRCUIT
4.7 mH 1 20 mF LS4148 2 3 SI9160 VDD 0.1 mF 100 k 0.1 mF 2.2 k 10 k N/C DMAX COMP FB NI VREF 0.1 mF GND VS DR DS PGND UVLOSET COSC ROSC ENABLE 56 pF 12 k To Power Management 1.2 k 0.1 mF 100 W 5600 pF 3.6 k 4 D1 S1 S1 G1 D2 8 7 6 5 LS4148 20 mF 6 V @ 500 mA
1 Cell LiIon
Si6801
S2 S2 G2
Document Number: 70029 S-40700--Rev. H, 19-Apr-04
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SI9160
Vishay Siliconix
ABSOLUTE MAXIMUM RATINGS
Voltages Referenced to GND. VDD, VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V PGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . "0.3 V Linear Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to VDD +0.3 V Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to VDD +0.3 V Peak Output Drive Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350 mA Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65 to 150_C Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150_C Power Dissipation (Package)a 16-Pin TSSOP (Q Suffix)a, b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 925 mW Thermal Impedance (QJA)a 16-Pin TSSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135_C/W Notes a. Device mounted with all leads soldered or welded to PC board. b. Derate 7.4 mW/_C above 25_C.
* . Exposure to Absolute Maximum rating conditions for extended periods may affect device reliability. Stresses above Absolute Maximum rating may cause permanent damage. Functional operation at conditions other than the operating conditions specified is not implied. Only one Absolute Maximum rating should be applied at any one time.
SPECIFICATIONS
Test Conditions Unless Otherwise Specifieda Parameter Reference
Output Voltage VREF IREF = -10 mA TA = 25_C 1.455 1.477 1.50 1.545 1.523 V
Limits
B Suffix -25 to 85_C
Symbol
2.7 V v VDD, VS v 6.0 V, GND = PGND
Minb
Typ
Maxb
Unit
Oscillator
Maximum Frequencyc Oscillator Frequency Accuracy ROSC Peak Voltage Voltage Stabilityc Temperature Stabilityc VROSC Df/f 4 V v VDD v 6 V, Ref to 5 V, TA = 25_C Referenced to 25_C -8 "5 fMAX VDD = 5 V, COSC = 47 pF, ROSC = 5.0 kW VDD = 3.0 V, fOSC = 1 MHz (nominal) COSC = 100 pF, ROSC = 7.0 kW, TA = 25_C 2.0 -15 1.0 8 15 MHz % V %
Error Amplifier (COSC = GND, OSC DISABLED)
Input Bias Current Open Loop Voltage Gain Offset Voltage Unity Gain Bandwidthc Output Current Power Supply Rejectionc IB AVOL VOS BW IOUT PSRR Source (VFB = 1 V, NI = VREF) Sink (VFB = 2 V, NI = VREF) 4 V < VDD < 6 V 0.4 VNI = VREF VNI = VREF , VFB = 1.0 V -1.0 47 -15 55 0 10 -2.0 0.8 60 -1.0 15 1.0 mA dB mV MHz mA dB
UVLOSET Voltage Monitor
Under Voltage Lockout Hysteresis UVLO Input Current VUVLOHL VUVLOLH VHYS IUVLO(SET) UVLOSET High to Low UVLOSET Low to High VUVLOLH - VUVLOHL VUVLO = 0 to VDD -100 0.85 1.0 1.2 200 100 1.15 V mV nA
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Document Number: 70029 S-40700--Rev. H, 19-Apr-04
SI9160
Vishay Siliconix
SPECIFICATIONS
Test Conditions Unless Otherwise Specifieda Parameter Output Drive (DR and DS)
Output High Voltage Output Low Voltage Peak Source Output Current Peak Sink Output Current Break-Before-Make VOH VOL ISOURCE ISINK tBBM VDD = 2.7 V VS = 5.3 V IOUT = -10 mA IOUT = 10 mA 250 5.15 5.2 0.06 -300 300 40 0.15 -250 V
Limits
B Suffix -25 to 85_C
Symbol
2.7 V v VDD, VS v 6.0 V, GND = PGND
Minb
Typ
Maxb
Unit
VDD = 2.7 V, VS = 5 3 V 27V 5.3 VDD = 6.0 V
mA ns
Logic
ENABLE Delay to Output ENABLE Logic Low ENABLE Logic High ENABLE Input Current tdEN VENL VENH IEN ENABLE = 0 to VDD 0.8 VDD -1.0 1.0 ENABLE Rising to OUTPUT, VDD = 6.0 V 1.4 0.2 VDD ms V mA
Duty Cycle
Maximum Duty Cycle DMAX/SS Input Current CYCLEMAX IDMAX VDD = 6.0 V DMAX = 0 to VDD -100 80 95 100 % nA
Supply
Supply Current Normal Mode Current--Normal Supply Current--Standby Mode IDD fOSC = 1 MHz ROSC = 7.0 kW ENABLE = Low VDD = 2.7 V VDD = 4.5 V 1.1 1.6 250 1.5 2.3 330 mA mA
Notes a. CSTRAY < 5 pF on COSC. After Start-Up, VDD of w 3 V. b. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet. c. Guaranteed by design, not subject to production testing.
TYPICAL CHARACTERISTICS (25_C UNLESS OTHERWISE NOTED)
1.515 1.510 1.505 V REF (V) 1.500 1.495 1.490 1.485 2 3
VREF vs. Supply Voltage
VREF with 10-mA Load
1.515 1.510 1.505 V REF (V) 1.500 1.495 1.490 1.485 -40
VREF vs. Temperature
VDD = 2.7 V
VDD = 5.0 V
4
5
6
7
-20
0
20
40
60
80
100
VDD - Supply Voltage (V) Document Number: 70029 S-40700--Rev. H, 19-Apr-04
T - Temperature (_C)
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SI9160
Vishay Siliconix
TYPICAL CHARACTERISTICS (25_C UNLESS OTHERWISE NOTED)
1.502
VREF vs. Load Current
80 60
Error Amplifier Gain and Phase
1.501 2.7 V Gain (dB) V REF (V) 1.500 3.6 V 1.499 5.0 V 1.498
0 Gain -30 Phase (deg) Phase -60 -90 -120
40 20 0 -20
6.0 V
1.497 0 20 40 60 80 100 VREF - Sourcing Current (mA)
-40 0.0001 0.001 0.01 0.1 1 10 100 f - Frequency (MHz)
-150
Supply Current vs. Supply Voltage and Temperature
21 20 19 I DD + I S (mA) 85_C 18 17 16 15 14 2 3 4 5 6 7 VDD - Supply Voltage (V) CL = 1000 pF ROSC = 7.0 kW COSC = 100 pF -25_C 25_C 230 225 220 Standby Current ( m A) 215 210 205 200 195 190 185 2
Standby Current vs. Supply Voltage and Temperature
TA = 85_C 25_C
-25_C
3
4
5
6
7
VDD - Supply Voltage (V)
600 500 400 300 200 100 0
DR and DS Sourcing Current vs. Supply Voltage
500
DR and DS Sinking Current vs. Supply Voltage
DR & DS Sourcing Current (mA)
DR & DS Sinking Current (mA)
DS DR
400
DS DR
300
200
100
0 2 3 4 5 6 7 2 3 4 5 6 7
VS - Supply Voltage (V) www.vishay.com
VS - Supply Voltage (V) Document Number: 70029 S-40700--Rev. H, 19-Apr-04
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SI9160
Vishay Siliconix
TYPICAL CHARACTERISTICS (25_C UNLESS OTHERWISE NOTED)
1.10 1.05 Switching Frequency (MHz) 1.00 0.95 0.90 0.85 248.4 kW 0.80 2 3 4 5 6 7 0.01 40 100 200 300 400
Switching Frequency vs. Supply Voltage
ROSC = 7.0 kW COSC = 100 pF Switching Frequency (MHz)
10.00
Frequency vs. ROSC/COSC
1.00
4.98 kW 12.07 kW 24.88 kW
0.10
49.7 kW 100.4 kW
VDD - Supply Voltage (V)
COSC - Capacitance (pF)
90 80 70 Duty Cycle (%) 60 50 40 30 20 10 0 0.8 VS = 5.3 V
Duty Cycle vs. DMAX
1 MHz 500 kHz
1.5 MHz
0.9
1.0
1.1
1.2 DMAX (V)
1.3
1.4
1.5
1.6
Document Number: 70029 S-40700--Rev. H, 19-Apr-04
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SI9160
Vishay Siliconix
PIN CONFIGURATION AND ORDERING INFORMATION
TSSOP-16
VDD N/C DMAX COMP FB NI VREF GND 1 2 3 4 5 6 7 8 Top View Order Number: SI9160BQ-T1 16 15 14 13 12 11 10 9 VS DR DS PGND UVLOSET COSC ROSC ENABLE
ORDERING INFORMATION
Part Number
SI9160BQ-T1 SI9160BQ-T1--E3
Temperature Range
-25 to 85_C
Package
TSSOP-16
PIN DESCRIPTION
Pin 1: VDD The positive power supply for all functional blocks except output driver. A bypass capacitor of 0.1 mF (minimum) is recommended. Pin 2: N/C There is no internal connection to this pin. Pin 3: DMAX Used to set the maximum duty cycle. Pin 4: COMP This pin is the output of the error amplifier. A compensation network is connected from this pin to the FB pin to stabilize the system. This pin drives one input of the internal pulse width modulation comparator. Pin 5: FB The inverting input of the error amplifier. An external resistor divider is connected to this pin to set the regulated output voltage. The compensation network is also connected to this pin. Pin 6: NI The non-inverting input of the error amplifier. In normal operation it is externally connected to VREF or an external reference. Pin 7: VREF This pin supplies a 1.5-V reference. Pin 8: GND (Ground) Pin 9: ENABLE A logic high on this pin allows normal operation. A logic low places the chip in the standby mode. In standby mode, normal
fOSC ] R
operation is disabled, supply current is reduced, the oscillator stops, and DS goes low while DR goes high. Pin 10: ROSC A resistor connected from this pin to ground sets the oscillator's capacitor (COSC) charge and discharge current. See the oscillator section of the description of operation. Pin 11: COSC An external capacitor is connected to this pin to set the oscillator frequency.
0.70 COSC (at VDD = 5.0 V)
OSC
Pin 12: UVLOSET This pin will place the chip in the standby mode if the UVLOSET voltage drops below 1.2 V. Once the UVLOSET voltage exceeds 1.2 V, the chip operates normally. There is a built-in hysteresis of 200 mV. Pin 13: PGND The negative return for the VS supply. Pin 14: DS This CMOS push-pull output pin drives the external n-channel MOSFET. This pin will be low in the standby mode. A break-before-make function between DS and DR is built-in. Pin 15: DR This CMOS push-pull output pin drives the external p-channel MOSFET. This pin will be high in the standby mode. A break-before-make function between the DS and DR is built-in. Pin 16: VS The positive terminal of the power supply which powers the CMOS output drivers. A bypass capacitor is required.
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Document Number: 70029 S-40700--Rev. H, 19-Apr-04
SI9160
Vishay Siliconix
FUNCTIONAL BLOCK DIAGRAM
VDD UVLOSET UVLO
1.5-V Reference Generator
VREF VREF VUVLO GND
VUVLO ENABLE VS COMP Error Amp NI FB DMAX + - + - - Logic and BBM Control Oscillator Driver PGND VS Driver PGND VS
DS
COSC ROSC
DR
PGND
TIMING WAVEFORMS
5V
ENABLE
0V
1.5 V DMAX VCOSC 1V
tBBM DS
DR
Document Number: 70029 S-40700--Rev. H, 19-Apr-04
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SI9160
Vishay Siliconix
OPERATION OF THE SI9160 BOOST CONVERTER
The SI9160 combined with optimized complementary MOSFETs provides the ideal solution to small, high efficiency, synchronous boost power conversion. Optimized for a 1-cell lithium ion, or 3-cell to 4-cell Nickel metal hydride battery, it is capable of switching at frequencies of up to 2 MHz. Combined with the Si6801, a complimentary high-frequency MOSFET, efficiencies of over 90% are easily achieved in a very small area. PWM Controller Startup The SI9160 implements a synchronous voltage mode PWM control topology and is especially designed for battery power conversion. Voltage-mode control results in the most efficient power conversion solution. Figure 1 below illustrates a schematic for a synchronous boost converter with an input range of 2.7 V to 5 V which covers the range of 1-cell LiIon and 3-cell or 4-cell NiMH/NiCd battery input respectively, and an output voltage of 6 V. Note the maximum input voltage is limited to the output voltage for a boost converter. The switching frequency is determined by an external capacitor and resistor connected to Cosc and Rosc pins. The graph on page 5 in the Typical Characteristics section shows Designed to operate with single cell Lithium Ion battery voltage, the SI9160 has an operating range of 2.7 V to 6.0 V. During start-up, the device requires 3.0 V to guarantee proper operation, although it will typically start up at less than 2.2 V. Once powered, SI9160 will continue to operate until the voltage at VDD is 2.7 V; at this point, the battery is basically dead. During start-up, power for the chip is provided by the battery through schottky diode D1 to VDD and VS pins. Once the converter is fully operating, supply power is provided by the converter output through diode D2, which overrides the D1 diode. This self perpetuating method of powering further improves the converter efficiency by utilizing higher gate drive to lower the on-resistance loss of the MOSFET. the typical Cosc and Rosc values for various switching frequency. SI9160 oscillator frequency can be easily synchronized to external frequency as long as external switching frequency is higher than the internal oscillator frequency. The synchronization circuit is a series resistor and capacitor fed into the Cosc pin of the SI9160. The synchronization pulse should be greater than 1.5 V in amplitude and a near square wave pulsed clock. Figure 1 shows typical values for the synchronization components.
1-Cell LiIon
D1 LS4148
D2 LS4148
ML C1 10 mF
ML C2 10 mF 1 D1 2 S1 3 S1 4 G1
4.7 mH
R5 100 k
SYNC
C10 0.33 mF
SI9160 C2 0.1 mF R3 2.2 k 1 2 3 4 5 6 7 8 VDD NC DMAX COMP FB NI VREF GND VS DR DS PGND UVLOSET COSC ROSC ENABLE 16 15 14 13 12 11 10 9
C10 0.1 mF
8 D2 7 S2 6 S2 5 G2
Si6801
R4 2.2 k
C3 0.1 mF R2, 270 W R1 10 k
R9 100 W C11 36 pF C8 5600 pF
R10 3.6 k C9 0.1 mF R11 1.2 k ML C3 10 mF ML C4 10 mF
C6 C4 22 pF 0.1 mF
C5 0.1 mF
R6 12 k
Power Amplifier
FIGURE 1. SI9160 Boost Converter
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SI9160
Vishay Siliconix
Another benefit of powering from the output voltage is it provides minimum load on the converter. This prevents the converter from skipping frequency pulses typically referred to as Burst or Pulse-Skipping modes. Pulse skipping mode could be dangerous, especially if it generates noise in RF, IF, or signal processing frequency bands. Enable and Under Voltage Shutdown The SI9160 is designed with programmable under-voltage lockout and enable features. These features give designers flexibility to customize the converter design. The under-voltage lockout threshold is 1.2 V. With a simple resistor divider from VDD, SI9160 can be programmed to turn-on at any VDD voltage. The ENABLE pin, a TTL logic compatible input, allows remote shutdown as needed. Gate Drive and MOSFETs The gate drive section is designed to drive the high-side p-channel switch and low-side n-channel switch. The internal 40 ns break-before-make (BBM) timing prevents both MOSFETs from turning-on simultaneously. The BBM circuit monitors both drive voltages, once the gate-to-source voltage drops below 2.5 V, the other gate drive is delayed 40-ns before it is allowed to drive the external MOSFET (see Figure 2 for timing diagram). This smart gate drive control provides additional assurance that shoot-through current will not occur.
N-Channel Turn-On N-Channel Turn-Off
5 ns/DIV, 2 V/DIV
5 ns/DIV, 2 V/DIV
Note the Speed These MOSFETs have switching speeds of <5 ns. This high speed is due to the fast, high current output drive of the SI9160 and the optimized gate charge of the Si6801.
FIGURE 3. Gate Switching Times
Stability Components A voltage mode boost converter is normally stabilized with simple lag compensation due to the additional 90_ phase lag introduced by the additional right hand plane zero, as well as having a duty factor dependent resonant frequency for the output filter. The stability components shown in Figure 1 have been chosen to ensure stability under all battery conditions while maintaining maximum transient response. To do this we have used a 2-pole-zero pair configuration (type 3 amplifier configuration). Figure 4 shows the bode plot for the above circuit, maintaining > 50_ phase margin over the entire battery voltage range.
CH1 CH3 CH2
CH4
+50 Phase Gain Gain (dB) CH1: COSC ; CH2: DS CH3: COMP; CH4: DR Phase Margin > 50_
+180_
0
0_
FIGURE 2. Gate Drive Timing Diagrams
The MOSFET used is the Si6801, an n- and p-channel in a single package TSSOP-8. The Si6801 is optimized to have very low gate charge and gate resistance. This results in a great reduction in gate switching power losses. The average time to switch on and off a MOSFET in a conventional structure is about 20 ns. The Si6801 will switch on and off in < 5 ns, see Figure 3.
Li Battery Voltage Low Charge 2.7 V -50 100
Li Battery Voltage Full Charge 4.0 V -180_
101
102
103
104
105
106
Frequency (Hz)
FIGURE 4. Stability, with 1-cell Li battery input, 5 V @ 600-mA output.
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Document Number: 70029 S-40700--Rev. H, 19-Apr-04
Phase (deg)
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SI9160
Vishay Siliconix
Energy Storage Components The input and output ripple voltage is determined by the switching frequency, and the inductor and capacitor values. The higher the frequency, inductance, or capacitance values, the lower the ripple. The efficiency of the converter is also improved with higher inductance by reducing the conduction loss in the switch, synchronous rectifier, and the inductor itself. In the past, Tantalum was the preferred material for the input and output capacitors. Now, with 2-MHz switching frequencies, Tantalum capacitors are being replaced with smaller surface mount ceramic capacitors. Ceramic capacitors have almost no equivalent series resistance (ESR). Tantalum capacitors have at least 0.1-W ESR. By reducing ESR, converter efficiency is improved while decreasing the input and output ripple voltage. With ceramic capacitors, output ripple voltage is a function of capacitance only. The equation for determining output capacitance is stated below.
IOUT @ (V OUT - VIN) C+V OUT @ DV RIPPLE @ f
efficiency. The equation that shows the critical inductance which separates continuous and discontinuous current mode at any given output current is stated below. This equation is also plotted in Figure 5 as a function of input voltage. Designed with small surface mount inductors and capacitors, the SI9160 solution can fit easily within a small space such as a battery pack. Another distinct advantage of a smaller converter size is that it reduces the noise generating area by reducing the high current path; therefore radiated and conducted noise is less likely to couple into sensitive circuits.
V IN 2 @ VOUT - VIN @ h 2 @ VOUT
2
L+
@ I OUT @ f
h = efficiency
0.7 Continuous Mode
0.6 Discontinuous Mode 0.5
VOUT = output voltage VIN = input voltage DVRIPPLE = desired output ripple voltage f = switching frequency The inductance value for the converter is a function of the desired ripple voltage and efficiency as stated below. In order to keep the ripple small and improve efficiency, the inductance needs to be large enough to maintain continuous current mode. Continuous current mode has lower RMS current compared to discontinuous current mode since the peak current is lower. This lowers the conduction loss and improves
L ( m H)
IOUT = output dc load current
0.4
h = 0.9 VOUT = 5 V IOUT = 0.5 A f = 1 MHz
0.3 2.5 3.0 3.5 VIN (V) 4.0 4.5
FIGURE 5. Continuous and Discontinuous Inductance Curve
RESULTS SECTION
The following section shows the actual results obtained with the circuit diagram shown in Figure 1. Efficiency The Figure 6 shows the efficiency of the above design at various constant switching frequencies. The frequencies were generated using a 3-V square wave of the desired frequency to the sync input to the circuit. The input voltage to the circuit is 3.6-V dc. Output Noise The noise generated by a dc-dc converter is always an issue within the mobile phone. The SI9160 offers two benefits.
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The noise spectrum is a constant, i.e. no random noise or random harmonic generation. The switching fundamental can be synchronized to a known frequency, e.g. 812.5 kHz which is 1/16-th of the GSM/DCS system clock, 1.23 MHz which is the channel spacing frequency for CDMA, etc. Figures 7 through 9 show the output noise and output spectrum analysis. Output Noise Spectrum Note there is no random noise, only switching frequency harmonics. This is very good news for the RF stages, where an unknown, or random noise spectrum will cause problems.
Document Number: 70029 S-40700--Rev. H, 19-Apr-04
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SI9160
Vishay Siliconix
100 90 80 Efficiency (%) 70 60 50 40 30 0.0 VIN = 3.6 VOUT = 5 V 0.2 0.4 0.6 0.8 1.0 CH2 f = 1 MHz f = 1.4 MHz f = 1.8 MHz CH1 f = 600 kHz
500 ns/DIV CH1: Output Ripple (50 mV/DIV) CH2: P- and N-Channel Drain Voltage (2 V/DIV)
Output Current (A)
FIGURE 6. Efficiency of SI9160 and Si6801 Boost converter at various fixed frequencies
FIGURE 7. Output noise of the SI9160 demo board
50 mV 5 mV <1 mV Noise Floor Switching Frequency = 1 MHz
1 kHz
10 kHz
100 kHz
1 MHz
10 MHz
100 MHz
FIGURE 8. Spectrum response for the SI9160 demo board output voltage
50 mV 5 mV <1 mV Noise Floor
Switching Frequency = 1 MHz
1 MHz
2 MHz
3 MHz
5 MHz
10 MHz
FIGURE 9. Higher resolution of noise spectrum
Conclusion Switching at high, known frequencies results in a smaller footprint while maintaining high efficiency. Efficiencies at high switching frequencies can be improved by using Si6801
Document Number: 70029 S-40700--Rev. H, 19-Apr-04
optimized low gate charge and low gate resistance MOSFET. Additionally, synchronization to an external high frequency clock eliminates or greatly reduces any radio interference concerns and pushes harmonics out beyond signal processing frequencies.
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